31 #ifndef _FLASH_DEMO_H_
32 #define _FLASH_DEMO_H_
35 #include "fsl_device_registers.h"
37 #include "SSD_Types.h"
38 #include "SSD_FTFx_Internal.h"
39 #include "SSD_FTFx_Common.h"
47 #if (defined(CPU_MK64FN1M0VMD12))
49 #define BUFFER_SIZE_BYTE 0x100
51 #define EE_ENABLE 0x00
52 #define RAM_ENABLE 0xFF
53 #define DEBUGENABLE 0x00
55 #define PSECTOR_SIZE 0x00001000
56 #define DSECTOR_SIZE 0x00001000
59 #define FTFx_REG_BASE 0x40020000
60 #define PFLASH_BLOCK_BASE 0x00000000
61 #define DEFLASH_BLOCK_BASE 0xFFFFFFFF
62 #define EERAM_BLOCK_BASE 0x14000000
64 #define PBLOCK_SIZE 0x00100000
65 #define EERAM_BLOCK_SIZE 0x00001000
71 #define SECURITY_LOCATION 0x408
72 #define BACKDOOR_KEY_LOCATION 0x400
74 #define PFLASH_IFR 0x3C0
75 #define DFLASH_IFR 0x3F8
77 #define EEE_DATA_SIZE_CODE 0x22
78 #define DE_PARTITION_CODE 0x03
83 #define READ_NORMAL_MARGIN 0x00
84 #define READ_USER_MARGIN 0x01
85 #define READ_FACTORY_MARGIN 0x02
96 #define PSWAP_INDICATOR_ADDR (PBLOCK_SIZE/PBLOCK_NUM - (2*FTFx_PSECTOR_SIZE))
99 #define PSWAP_LOWERDATA_ADDR (PSWAP_INDICATOR_ADDR + FTFx_PSECTOR_SIZE)
100 #define PSWAP_UPPERDATA_ADDR (PSWAP_LOWERDATA_ADDR + PBLOCK_SIZE/2)
103 #define FTFx_SWAP_STATE_UNINIT 0x0
104 #define FTFx_SWAP_STATE_READY 0x1
105 #define FTFx_SWAP_STATE_UPDATE 0x2
106 #define FTFx_SWAP_STATE_UPDATE_ERS 0x3
107 #define FTFx_SWAP_STATE_COMPLETE 0x4
109 #define CC_ISR_NUM 34
110 #define RDCOL_ISR_NUM 35
113 #define CACHE_DISABLE FMC_PFB0CR &= ~(FMC_PFB0CR_B0SEBE_MASK | FMC_PFB0CR_B0IPE_MASK | FMC_PFB0CR_B0DPE_MASK | FMC_PFB0CR_B0ICE_MASK | FMC_PFB0CR_B0DCE_MASK);\
114 FMC_PFB1CR &= ~(FMC_PFB1CR_B1SEBE_MASK | FMC_PFB1CR_B1IPE_MASK | FMC_PFB1CR_B1DPE_MASK | FMC_PFB1CR_B1ICE_MASK | FMC_PFB1CR_B1DCE_MASK);\
123 #elif (defined(CPU_MK22FN512VDC12))
125 #define BUFFER_SIZE_BYTE 0x100
127 #define EE_ENABLE 0x00
128 #define RAM_ENABLE 0xFF
129 #define DEBUGENABLE 0x00
131 #define PSECTOR_SIZE 0x800
132 #define DSECTOR_SIZE 0x800
135 #define FTFx_REG_BASE 0x40020000
136 #define PFLASH_BLOCK_BASE 0x00000000
137 #define DEFLASH_BLOCK_BASE 0xFFFFFFFF
138 #define EERAM_BLOCK_BASE 0xFFFFFFFF
140 #define PBLOCK_SIZE 0x00080000
141 #define EERAM_BLOCK_SIZE 0x00000000
146 #define SECURITY_LOCATION 0x40C
147 #define BACKDOOR_KEY_LOCATION 0x400
149 #define PFLASH_IFR 0xC0
178 #define CC_ISR_NUM 34
179 #define RDCOL_ISR_NUM 35
182 #define CACHE_DISABLE FMC_PFB0CR &= ~(FMC_PFB0CR_B0SEBE_MASK | FMC_PFB0CR_B0IPE_MASK | FMC_PFB0CR_B0DPE_MASK |FMC_PFB0CR_B0ICE_MASK | FMC_PFB0CR_B0DCE_MASK); \
183 FMC_PFB1CR &= ~(FMC_PFB1CR_B1SEBE_MASK | FMC_PFB1CR_B1IPE_MASK | FMC_PFB1CR_B1DPE_MASK |FMC_PFB1CR_B1ICE_MASK | FMC_PFB1CR_B1DCE_MASK);
195 #define ONE_KB 1024 //0x400: 10 zeros
196 #define TWO_KB (2*ONE_KB)
197 #define THREE_KB (3*ONE_KB)
198 #define FOUR_KB (4*ONE_KB)
199 #define FIVE_KB (5*ONE_KB)
200 #define SIX_KB (6*ONE_KB)
201 #define SEVEN_KB (7*ONE_KB)
202 #define EIGHT_KB (8*ONE_KB)
203 #define NINE_KB (9*ONE_KB)
204 #define TEN_KB (10*ONE_KB)
205 #define ONE_MB (ONE_KB*ONE_KB) //0x100000: 20 zeros
206 #define ONE_GB (ONE_KB*ONE_KB*ONE_KB) //0x40000000: 30 zeros
209 #define BLANK_DATA 0xFFFFFFFF
211 #define NORMAL_MARGIN_READ 0
212 #define USER_MARGIN_READ 1
214 #define UPPER_BLOCK_START_ADDRESS (flashSSDConfig.PFlashBlockBase + BYTE2WORD(flashSSDConfig.PFlashBlockSize/PBLOCK_NUM))
215 #define LOWER_BLOCK_START_ADDRESS (flashSSDConfig.PFlashBlockBase)
217 #define SWAP_STATUS_BIT \
218 (REG_READ(FTFx_REG_BASE + FTFx_SSD_FCNFG_OFFSET) & FTFE_FCNFG_SWAP_MASK)
219 #define DEMO_LOCATIONS_ARE_BLANK \
220 ((READ32(PSWAP_LOWERDATA_ADDR) == 0xFFFFFFFF) && (READ32(PSWAP_UPPERDATA_ADDR) == 0xFFFFFFFF))
229 UINT32 flash_swap(
void);
230 void run_flash_swap(
void);
231 void print_swap_application_data(
void);
void callback(void)
Definition: flash_demo.c:462
void ErrorTrap(UINT32 ret)
Definition: flash_demo.c:445
void print_welcome_message(void)
UINT32 RelocateFunction(UINT32 dest, UINT32 size, UINT32 src)